A time to digital converter (TDC) is a circuit known in the art to detect phase offset (such as jitter) between two signals, e.g., a control signal of a phase locked loop and a reference clock signal.
FIG. 1 is a block diagram of a known TDC in a configuration known as a Vernier delay line. The principles of this TDC 100 are described in U.S. Pat. Pub. No. 2009/0225631 by Shimizu et al., “Time-To-Digital Converter,” which is hereby incorporated by reference herein in its entirety. The TDC 100 has a first delay line in which a sequence of delay cells 114 are arranged to sequentially delay an original clock CK. Each delay cell 114 delays its input by a predetermined delay amount τ1, and a plurality of delay taps CK1, CK2, CK3, . . . are provided to the data (D) inputs of corresponding D-type flip flops 116. A signal SC to be measured is provided to a second delay line in which each delay cell in a sequence of delay cells 115 delays its input by a predetermined delay amount τ2, where τ1 is typically greater than τ2. The first and second delay lines may be implemented using pairs of inverters, for example. Successive taps from the second delay line are provided as clock inputs SC1, SC2, SC3, . . . to corresponding flip flops 116.
Because τ1>τ2, signals in the sequence SC1, SC2, SC3, . . . are advanced relative to signals in the sequence CK1, CK2, CK3, . . . . In other words, if a rising clock edge of CK1 occurs before a rising clock edge of SC1, there will be a point along the first and second delay lines at which a delay tap from the second sequence 115 “catches up” to a corresponding delay tap from the first sequence 114. In this example, the Q outputs from flip flops 116 are ‘1’ up to this point and ‘0’ thereafter. An encoder circuit 117 receives the Q outputs and encodes a position at which such crossover occurs, and the encoded result represents the jitter of the signal SC to be measured with respect to the reference clock CK. For example, if 2N flip flops are employed, encoder 117 provides an N-bit encoded value representing a jitter of signal SC.
Conventional TDC 100 has certain deficiencies. Due to variations in process, voltage, and temperature, the total delay of a delay line may be different than the desired value, resulting in certain disadvantageous effects. For example, a variation in the total delay of delay cells 115 may result in undesirable phase noise in the encoded signal indicating jitter. Furthermore, mismatch between individual delay cells may result in other disadvantageous effects. For example, variations in the delays of delay cells 115 may result in harmonic “spurs” (spurious noise components) in a frequency response of the encoded jitter signal. Both these disadvantageous effects impair the ability to accurately measure jitter.
FIG. 2 is a block diagram of a known timing circuit 200 that seeks to address the phase noise and spur problems discussed above. Timing circuit 200 is fully described in Temporiti et al., “A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques,” IEEE Journal of Solid-State Circuits, Vol. 44, No. 3, pp. 824-34, March 2009, and only a brief description of the principles of that circuit follows. Circuit 200 includes a TDC 230 as well as feedback to control delay cells in the TDC 230. A signal CKDCO to be measured, provided by a digitally controlled oscillator, is provided to D inputs of D-type flip flops 240-1, 240-2, . . . , 240-N (generally 240). A reference clock signal CKREF is provided to a clock doubler 210 that also receives input from a pseudorandom number generator (PRNG) 220. The reason for the presence of the clock doubler 210 and the PRNG 220 will be apparent shortly. Much as in TDC 100, the output from the clock doubler 210 is provided to delay cells 250-1, 250-2, . . . , 250-N (generally 250), and successive delay taps are provided to clock inputs of corresponding D flip flops 240. The output from TDC 230 is an encoded signal representing a jitter between CKDCO and CKREF, and this output is shown in FIG. 2 as emanating from the last flip flop 240-N for convenience, although it is understood that an encoder (not shown) provides encoding much as in FIG. 1.
A calibration module 260, comprising a grouper 262 to process groups of bits, an adder 264, a low pass filter 266, and a quantizer 268, provides a calibration signal based on the encoded output from TDC 230. A correction module 270 provides N correction signals that are added to the calibration signal at adders 280-1, 280-2, . . . , 280-N and used to control delay cells, e.g., via principles of variable capacitance. Thus, calibration and correction loops are present in a feedback configuration. The effects of the calibration and correction modules are to reduce phase noise and spurs, respectively. The clock doubler 210 is needed because 50% of available cycles are set aside for calibration. The PRNG 220 is used to inject pseudorandom jitter to improve performance, including by reducing unwanted periodicities.
The calibration loop in circuit 200 collects many input signals (groups of five signals for integration), resulting in a relatively long calibration time. Circuit 200 needs multipliers in correction module 270, requiring large silicon area in a practical embodiment. Clock doubler 210 and PRNG 220 area also needed, resulting in high power consumption, which decreases performance in terms of noise. Because of the clock doubler 210 and the use of 50% of samples for calibration, the operation speed of circuit 200 is twice the input frequency.
FIG. 3 is a block diagram of another known timing circuit. Circuit 300 is described in Chang et al., “A fractional spur free all-digital PLL with loop gain calibration and phase noise cancellation for GSM/GPRS/EDGE,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 222-23, 598, February 2008. Circuit 300 includes a phase frequency detector and cyclic TDC 310 that receives a reference clock CKREF and a feedback signal CKFB. As part of a phase locked loop, circuit 300 provides a digital loop filter 330, a digitally controlled oscillator 332, and a divider 234 that provides the feedback signal CKFB. A sigma-delta modulator 340 is used to randomly change a frequency division value of the divider 234 to reduce spurious noise. Sigma-delta modulators are known in the art and are described at, e.g., U.S. Pat. No. 7,279,990, by Hasegawa, “Sigma-Delta Modulator for PLL Circuits,” which is hereby incorporated by reference herein in its entirety. Sigma-delta modulator 340 receives a numerator value F that is accumulated in a manner that causes the frequency division ratio of divider 234 to vary. A scale factor 370, which is the ratio of an output clock period to the delay time of a delay cell, is used to update the phase locked loop. The scale factor replaces the calibration loop of circuit 200 for phase noise mitigation. Circuit 300 does not contain a correction loop, resulting in phase noise performance of circuit 300 being worse than that of circuit 200. With adders 320, 342 and 350, delay element 360, scale factor 370, and multiplier 380, the input to the digital loop filter 330 is controlled in a manner that provides some phase noise cancellation. The use of a cyclic TDC, in which the output of a last delay cell feeds back to an input of a first delay cell, reduces the number of delay cells but induces in-band phase noise. The use of a multiplier 380 increases silicon area. The performance of circuit 300 in terms of spurs and phase noise is worse than that of circuit 200.
It is desirable to employ TDC timing techniques that reduce phase noise and spurs with reduced circuit complexity and increased efficiency.